FastRMT - High-Speed Programmable Data Plane

First open-source FPGA-level RMT architecture implementation

FastRMT is the first open-source FPGA-level RMT (Reconfigurable Match-Action Table) architecture implementation, supporting 100Gbps line-rate processing with microsecond-level latency.

Key Features

  • High Performance: 100Gbps line-rate packet processing
  • Low Latency: Microsecond-level processing delay
  • Fully Programmable: Supports custom packet processing pipelines
  • Open Source: First open-source FPGA implementation of RMT architecture

Impact

  • Adopted by Xilinx OpenNIC, Maipu Smart NIC, and satellite switching chips
  • Published in CCF-A journal Journal of Computer Research and Development (2024)
  • Presented at NSDI 2022
  1. FastRMT: A High-Speed Data Plane Programmable System for Microarchitecture Innovation - Journal of Computer Research and Development, 2024
  2. Isolation Mechanisms for High-Speed Packet-Processing Pipelines - USENIX NSDI 2022