Projects

Research Projects

Here are a part of the research projects I have been working on.

FastRMT - High-Speed Programmable Data Plane

First open-source FPGA-level RMT architecture implementation

FastRMT is the first open-source FPGA-level RMT (Reconfigurable Match-Action Table) architecture implementation, supporting 100Gbps line-rate processing with microsecond-level latency.

Key Features:

  • 100Gbps line-rate packet processing
  • Microsecond-level processing delay
  • Fully programmable pipelines
  • Open source

Impact: Adopted by many interesting opensource projects like Menshen.

FlexTSN - Time-Sensitive Networking

Flexible TSN switching model with programmable scheduling

FlexTSN addresses the conflict between deterministic scheduling and hardware overhead in Time-Sensitive Networking.

Key Innovations:

  • AIAO (Any-In-Any-Out) programmable scheduling primitive
  • Memory-efficient design
  • IEEE 802.1Qbv compliant

Impact: Core architecture integrated into Yinhe Hengxin I TSN switching chip.

FAST Framework (IWQoS 2019)

Hardware-software co-design network acceleration teaching platform

FAST (FPGA-Accelerated Switching and Testing) is designed for both research and education in network systems.

Adoption:

  • Beijing University of Posts and Telecommunications
  • University of Electronic Science and Technology of China
  • Southeast University
  • National University of Defense Technology

Impact: Supported research leading to publications in SIGCOMM, ToN, and other top venues.